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| om .c IntelU 4 StrataFlash Wireless Memory et System (LV18/LV30 SCSP) e h768-Mbit LVQ Family with Asynchronous Static RAM aS Datasheet at .D Product Features w w w m o .c U t4 e e h S ta a .D w w w Device Architecture -- Code and data segment: 128- and 256Mbit density; PSRAM: 32- and 64-Mbit density; SRAM: 8 Mbit density. -- Top or bottom parameter configuration. -- Asymmetrical blocking structure. -- 16-KWord parameter blocks (Top or Bottom); 64-K Word main blocks. -- Zero-latency block locking. -- Absolute write protection with block lock down using F-WP#. Device Voltage -- Core: VCC = 1.8 V (typ). -- I/O: VCCQ = 1.8 V or 3.0 V (typ). Device Concurrent Operations (3 Dies) -- Buffered EFP: 600 KB per second. -- Erase Performance: 384 KB per second (main blocks). Device Packaging -- 88 balls (8 x 10 active ball matrix). -- Area: 8 x 10 mm or 8 x 11 mm. -- Height: 1.0 mm to 1.4 mm. Quality and Reliability -- Extended Temp: -25 C to +85 C. -- Minimum 100 K flash block erase cycle. xRAM Performance -- PSRAM at 1.8 V I/O : 85 ns initial access, 30 ns async page reads; 65 ns initial access, 18 ns async page. -- SRAM at 1.8 or 3.0 V I/O: 70 ns initial access. Flash Performance -- Code Segment at 1.8 V I/O: 85 ns initial access; 25 ns async page read; 14 ns sync reads (tCHQV); 54 MHz CLK. -- Data Segment at 1.8 V I/O: 170 ns initial access; 55 ns async page read. Flash Architecture -- Hardware Read-While-Write/Erase. -- 8-Mbit or 16-Mbit Multi-Partition. -- 2-Kbit One-Time Programmable (OTP) Protection Register. -- Software Read-While-Write/Erase. -- Single Full-Die Partition size. Flash Software -- Intel FDI, Intel PSM, and Intel VFM. -- Common Flash Interface (CFI). -- Basic/Extended Command Set. The Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family with Asynchronous Static RAM device offers a high performance code and large embedded data segment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13 m ETOXTM VIII flash technology. The code segment flash die features 1.8 V low-power operations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase, asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V low-power operations optimized for cost sensitive asynchronous data applications. This device integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package compatible with other SCSP families using the QUAD+ ballout package. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. om .c 4U et he aS at .D w w w 253852-002 December 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LV18/LV30 SCSP datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. *Other names and brands may be claimed as the property of others. Copyright (c) Intel Corporation, 2003 2 Datasheet Contents Contents 1.0 Introduction....................................................................................................................................5 1.1 1.2 1.3 2.0 3.0 2.1 3.1 3.2 3.3 3.4 3.5 4.0 5.0 4.1 5.1 5.2 6.0 7.0 6.1 7.1 7.2 7.3 7.4 7.5 7.6 8.0 9.0 Nomenclature .......................................................................................................................5 Acronyms ..............................................................................................................................7 Conventions..........................................................................................................................7 Device Description ................................................................................................................9 One- and Two-Die SCSP....................................................................................................11 Four-Die SCSP ...................................................................................................................12 One-Die Intel UT-SCSP ...................................................................................................13 Two-Die Intel UT-SCSP ...................................................................................................14 Three-Die Intel UT-SCSP ................................................................................................15 Signal Descriptions .............................................................................................................18 Absolute Maximum Ratings ................................................................................................21 Operating Conditions ..........................................................................................................22 DC Current Characteristics .................................................................................................23 SCSP Device AC Test Conditions ......................................................................................25 SRAM and PSRAM Capacitance........................................................................................25 SRAM AC Read Specifications...........................................................................................25 SRAM AC Write Specifications ...........................................................................................27 PSRAM AC Read Specifications ........................................................................................30 PSRAM AC Write Specifications ........................................................................................32 Functional Overview .....................................................................................................................9 Package Information ...................................................................................................................11 Ballout and Signal Descriptions ................................................................................................16 Maximum Ratings and Operating Conditions...........................................................................21 Electrical Specifications .............................................................................................................23 AC Characteristics ......................................................................................................................25 Power and Reset Specifications ................................................................................................34 Design Guide: Operation Overview ...........................................................................................35 9.1 9.2 Bus Operations ...................................................................................................................35 Flash Device Commands and Command Definitions .........................................................36 Datasheet 3 Contents 10.0 Flash Read Operation ................................................................................................................. 37 11.0 Flash Program Operation ........................................................................................................... 37 12.0 Flash Erase Operation ................................................................................................................ 37 13.0 Flash Suspend and Resume Operations................................................................................... 37 14.0 Flash Block Locking and Unlocking Operations...................................................................... 37 15.0 Flash Protection Register Operation ......................................................................................... 37 16.0 Flash Configuration Operation................................................................................................... 37 17.0 Dual Operation Considerations.................................................................................................. 38 17.1 17.2 17.3 Product Configurations and Memory Partitioning ............................................................... 38 Product Segment Unique Features .................................................................................... 39 Flash Die Memory Map....................................................................................................... 40 18.0 PSRAM Operations...................................................................................................................... 45 18.1 18.2 PSRAM Power-up Sequence and Initialization................................................................... 45 PSRAM Mode Register....................................................................................................... 45 18.2.1 PSRAM Mode Register Setting ............................................................................. 46 18.2.2 Cautions for Setting PSRAM Mode Register ......................................................... 47 PSRAM Low-Power Mode .................................................................................................. 48 18.3 Appendix A Write State Machine ........................................................................................................ 49 Appendix B Common Flash Interface................................................................................................. 49 Appendix C Flash Flowcharts ............................................................................................................. 49 Appendix D Additional Information .................................................................................................... 50 Appendix E Ordering Information....................................................................................................... 51 Revision History Date 10/03r 12/03 Revision -001 -002 Initial Release In the Valid Combinations Table: Added line item mehcanical and ordering information for 256L+256V+64P+64P. Deleted the TBD 5-die stack option. Revised the Matrix table. Description 4 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 1.0 Introduction This document provides information about the Intel StrataFlash(R) Wireless Memory System (LV18/ LV30 SCSP); 768-Mbit LVQ Family with Asynchronous Static RAM device, including information on the features, characteristics, operations, and specifications for: * Code and data segment flash dies * SRAM and PSRAM dies The intent of this document is to provide information where this 768-Mbit LVQ Family with Asynchronous Static RAM Stacked Chip Scale Package (SCSP) device differs from the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP); 1024-Mbit LV Family device. Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024Mbit LV Family Datasheet (order number 253854) for flash product details not included in this document. 1.1 Nomenclature 0x 0b Byte CFI DU ETOX k (noun) Kb KB Kword M (noun) Mb MB OTP RCR RFU SCSP SR SRD Word 1.8 V Core 1.8 V I/O Asserted Deasserted High-Z Low-Z Hexadecimal prefix Binary prefix 8 bits Common Flash Interface Don't Use EPROM Tunnel Oxide 1 thousand 1024 bits 1024 bytes 1024 words 1 million 1,048,576 bits 1,048,576 bytes One-time Programmable Read Configuration Register Reserved for Future Use Stacked Chip Scale Package Status Register Status Register Data 16 bits range of 1.7 V - 1.95 V range of 1.7 V - 1.95 V Signal with logical voltage level VIL, or enabled Signal with logical voltage level VIH, or disabled Tri-stated or High Impedance Driven Datasheet 5 768-Mbit LVQ Family with Asynchronous Static RAM Non-Array Reads Program Write Block Parameter block Main block Top parameter Flash reads which return flash Device Identifier, CFI Query, Protection Register and Status Register information An operation to Write data to the flash array Bus cycle operation at the inputs of the flash die, in which a command or data are sent to the flash array Group of cells, bits, bytes or words within the flash memory array that get erased with one erase instruction Any 16-Kword flash array block. Any 64-Kword flash array block. Previously referred to as a top-boot device, a device with flash parameter partition located at the highest physical address of its memory map for processor system boot up. Previously referred to as a bottom-boot device, a device with flash parameter partition located at the lowest physical address of its memory map for processor system boot up. Bottom parameter Bottom-Top parameter Stacked-CSP device configuration of two flash dies in the same segment arranged with the parameter partitions located at the lowest and highest physical address of its memory map. Partition Parameter partition Main partition Die Segment A group of flash blocks that shares common status register read state. A flash partition containing parameter and main blocks. A flash partition containing only main blocks. Individual physical flash die used in a stacked-CSP memory subsystem device A section of the SCSP memory subsystem divided for different operating characteristics. The SCSP memory subsystem has three segments: a code segment, a data segment, and an xRAM segment. A segment that contains one or two flash memory dies optimized for fast code or data reads. Each die features multi-partition synchronous read-while-write or burst read-while-erase capability. A segment contains one or two flash memory dies optimized for large embedded data. Each die feature single-partition asynchronous read, write, and erase operations. A segment contains one or two xRAM memory dies. The xRAM combinations could include SRAM, PSRAM, or LPSDRAM. A stacked memory integration concept made up of multiple memory dies arranged in Code, Data, and xRAM segments. An individual flash die or a flash + xRAM SCSP. Code segment Data segment xRAM segment Subsystem Device 6 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 1.2 Acronyms Buffered-EFP CUI OTP PLR PR RCR RFU SR WSM APS CFI MLC technology RWE RWW Buffered Enhanced Factory Programming Command User Interface One-Time Programmable Protection Lock Register Protection Register Read Configuration Register Reserved for Future Use (all unused active signals in a package ballout) Status Register Write State Machine Automatic Power Savings Common Flash Interface Multi-Level-Cell technology Read-While-Erase Read-While-Write 1.3 Conventions VCC VCC Set Clear 0x 0b SR[4] D[15:0] A5 Signal or voltage connection Signal or voltage level Logical one (1) Logical zero (0) Hexadecimal number prefix Binary number prefix Denotes an individual flash status register bit, in this case bit 5 of SR[7:0]. Denotes a group of similarly named signals, such as data bus. Denotes one element of a signal group membership, in this case address bit 5. F[3:1]-CE#, F[2:1]-OE# This is the method used to refer to more than one chip-enable or output enable at the same time. When each is referred to individually, the reference will be F1-CE# and F1-OE# (for die #1), F2-CE# and F2-OE# (for die #2), and F3-CE# and F3-OE#(for die #3). "F" denotes the flash specific signal and "CE#" is the root signal name of the flash die. Other Datasheet 7 768-Mbit LVQ Family with Asynchronous Static RAM notation includes: "S" to denote SRAM, "P" to denote PSRAM, "D" to denote LPSDRAM, and "R" to denote common RAM type signal names. ADV# Denotes a global signal of the device, Address Valid because there is no die specific reference. 8 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 2.0 Functional Overview This section provides an overview of the code and embedded data segment features and capabilities of the 768-Mbit LVQ Family with Asynchronous Static RAM device. 2.1 Device Description The 768-Mbit LVQ Family with Asynchronous Static RAM device incorporates flash dies used as code segment flash memory and large embedded data segment flash memory, along with xRAM for a high performance, cost-effective high density memory system solution. This stacked device uses the latest Intel StrataFlash(R) Wireless Memory System on 0.13 m ETOXTM VIII process technology. The code segment is a high performance, multi-partition, synchronous burst-mode Read-WhileWrite (RWW) or Read-While-Erase (RWE) flash memory die, while the large, embedded data segment is a cost efficient, single-partition, asynchronous flash memory die. The package for this device is available in a QUAD+ ballout, which supports flash only or flash + PSRAM and/or SRAM stacked memory combinations. The SCSP in a QUAD+ ballout with a 0.8 mm ball pitch, 8x10 active ball matrix supports a memory subsystem up to 66 MHz on a x16-bit bus width. See Figure 1, "LV18/LV30 device family block diagram" on page 9 for device block diagram. Figure 1. LV18/LV30 device family block diagram LVQ Family Code Segment F1-CE# F-WE# F[2:1]-OE# F-RST# F3-CE# Flash Die # 1 (128- or 256-Mbit) Data Segment Flash Die # 2 (128- or 256-Mbit) F2-CE# F-VCC F-VPP Optional Flash Die # 3 (128- or 256-Mbit) Optional Flash Die # 3 (128- or 256-Mbit) F3-CE# VSS F-WP# CLK ADV# WAIT S-CS1# S-CS2 P[2:1]-CS# R-OE# R-WE# Die # 1 32- 64- or 128Mbit PSRAM Die # 2 64- or 128-Mbit PSRAM Die # 3 8-Mbit SRAM VCCQ A[MAX:MIN] D[15:0] xRAM Segment S-VCC P-VCC R-UB# R-LB# P-MODE / P-CRE Datasheet 9 768-Mbit LVQ Family with Asynchronous Static RAM The 768-Mbit LVQ Family with Asynchronous Static RAM device consists of a 1.8 V flash memory device with 1.8 V and 3.0 V I/O options. As shown in Figure 1, "LV18/LV30 device family block diagram" on page 9, the device is available with a minimum of one flash die each per code segment and data segment (flash die # 1 and flash die #2). An optional third flash die is available for either the code or data segment. See Table 1, "768 Mbit LVQ Family Matrix" on page 10 for possible combinations. Designed for low-voltage systems, the LVQ supports read operations with F-VCC at 1.8 V, and erase and program operations with F-Vpp at 1.8 V. Buffered Enhanced Factory Programming (Buffered-EFP) provides the fastest flash array programming performance, with elevated F-VPP at 9.0 V to increase factory throughput. With F-VPP at 1.8 V, F-Vcc and F-Vcc can be tied together for a simple, ultra-low-power design. In addition to voltage flexibility, a dedicated F-VPP connection provides complete data protection when F-Vpp VPPLK. The Intel StrataFlash(R) Wireless Memory System provides data security through its individual zerolatency block lock capability. Each memory block can be unlocked, locked, or locked-down by hardware or software control. Individualized F-CE# control allows the user to manage which flash die is asserted, furthering the flexibility of power management while controlling data integrity per segment with F-WP#. The F[2:1]-OE# in LVQ products with QUAD+ ballout are common internally Table 1. 768 Mbit LVQ Family Matrix Line Item 1.8 V I/O 256L18 + 256V18 3.0 V I/O 256L30 + 256V30 64PS + 64PS None 11x13x1.4 8x11x1.2 1 1 Flash Components 256L18 + 256L18 None RAM Components Package Size 8x11x1.2 Notes 1 NOTES: 1. Available in Top or Bottom Configurations. 10 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 3.0 Package Information The 768-Mbit LVQ Family with Asynchronous Static RAM device is available with various die combinations in both the standard Stacked Chip Scale Package (SCSP) and the Intel(R) Ultra-Thin Stacked Chip Scale Package (Intel(R) UT-SCSP). 3.1 One- and Two-Die SCSP Figure 2. Mechanical Specifications for One/Two-Die SCSP (8x10 mm) 8x10x1.2Q A1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1 Top View - Ball Down A2 A1 Bottom View - Ball Up A Y Draw ing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 9.900 7.900 Millimeters Nom Max 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600 Notes Min 0.0079 Inches Nom Max 0.0472 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.0167 0.3976 0.3189 1.100 0.500 0.100 1.300 0.700 0.0433 0.0197 0.0039 0.0512 0.0276 Datasheet 11 768-Mbit LVQ Family with Asynchronous Static RAM 3.2 Four-Die SCSP Figure 3. Mechanical Specifications for Four-Die SCSP (11x13 mm) A1 Index Mark 1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E 8 7 6 5 4 3 2 1 S1 S2 A B C D E F G H J K L M e Top View - Ball Down A2 A1 Bottom View - Ball Up A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 12.900 10.900 Millimeters Nom Max 1.400 1.070 0.375 13.000 11.000 0.800 88 2.700 2.100 Notes Min 0.0079 Inches Nom Max 0.0551 0.425 13.100 11.100 0.0128 0.5079 0.4291 0.0421 0.0148 0.5118 0.4331 0.0315 88 0.1063 0.0827 0.0167 0.5157 0.4370 2.600 2.000 0.100 2.800 2.200 0.1024 0.0787 0.0039 0.1102 0.0866 12 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 3.3 One-Die Intel UT-SCSP Figure 4. Mechanical Specifications for One-Die Intel(R) UT-SCSP (8x11 mm) A1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e T op View - Ball Down A2 A1 Bottom View - Ball Up A Y Drawing not to scale. Note: Dimensions A1, A2, and b are preliminary Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body W idth Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.117 0.300 10.900 7.900 0.740 0.350 11.00 8.00 0.80 88 1.200 1.100 0.400 11.100 8.100 Millimeters Nom Max 1.00 Notes Min 0.0046 0.0118 0.4291 0.3110 0.0291 0.0138 0.4331 0.3150 0.0315 88 0.0472 0.0433 0.0157 0.4370 0.3189 Inches Nom Max 0.0394 1.100 1.000 0.100 1.300 1.200 0.0433 0.0394 0.0039 0.0512 0.0472 Datasheet 13 768-Mbit LVQ Family with Asynchronous Static RAM 3.4 Two-Die Intel UT-SCSP Figure 5. Mechanical Specifications for Two-Die Intel(R) UT-SCSP (8x11 mm) A1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1 Top View - Ball Down A2 A1 Bottom View - Ball Up A Y Draw ing not to scale. Dimensions Pa ckage Height Ball Height Pa ckage Body Thickne ss Ball (Lead) Width Pa ckage Body Length Pa ckage Body Width Pitch Ball (Lead) Count Se ating Plane Coplanarity Corne r to Ball A1 Distance Along E Corne r to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 10.900 7.900 Millimete rs Nom Max 1.200 0.860 0.375 11.000 8.000 0.800 88 1.200 1.100 Notes Min 0.0079 Inches Nom Max 0.0472 0.425 11.100 8.100 0.0128 0.4291 0.3110 0.0339 0.0148 0.4331 0.3150 0.0315 88 0.0472 0.0433 0.0167 0.4370 0.3189 1.100 1.000 0.100 1.300 1.200 0.0433 0.0394 0.0039 0.0512 0.0472 14 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 3.5 Three-Die Intel UT-SCSP Figure 6. Mechanical Specifications for Three-Die Intel(R) UT-SCSP (8x11 mm) A1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1 Top View - Ball Down A2 A1 Bottom View - Ball Up A Y Draw ing not to scale. Note:DimensionsA1, A2,andb arepreliminary Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.117 0.300 10.900 7.900 0.910 0.350 11.00 8.00 0.80 88 1.200 1.100 0.400 11.100 8.100 Millimeters Nom Max 1.20 Notes Min 0.0046 0.0118 0.4291 0.3110 0.0358 0.0138 0.4331 0.3150 0.0315 88 0.0472 0.0433 0.0157 0.4370 0.3189 Inches Nom Max 0.0472 1.100 1.000 0.100 1.300 1.200 0.0433 0.0394 0.0039 0.0512 0.0472 Datasheet 15 768-Mbit LVQ Family with Asynchronous Static RAM 4.0 Ballout and Signal Descriptions Figure 7, "QUAD+ Signal Ballout for LVQ Device Family" shows the signal ballout for the 768Mbit LVQ Family with Asynchronous Static RAM device, ideal for space-constrained board applications and allowing density upgrades without PCB redesign. The user is responsible to adapt for density upgrade flexibility in the PCB design. 16 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Figure 7. QUAD+ Signal Ballout for LVQ Device Family 1 2 3 4 5 6 7 8 A DU DU DU DU B A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 D A3 A17 A24 F-VPP, F-VPEN R-WE# P1-CS# A9 A13 E A2 A7 A25 F-WP# ADV# A20 A10 A15 F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 G A0 D8 D2 D10 D5 D13 WAIT F2-CE# H R-OE# D0 D1 D3 D12 D14 D7 F2-OE# J S-CS1# F1-OE# D9 D11 D4 D6 D15 VCCQ K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE L VSS VSS DU VCCQ F1-VCC VSS VSS VSS DU VSS DU M DU Top View - Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific Datasheet 17 768-Mbit LVQ Family with Asynchronous Static RAM 4.1 Signal Descriptions Table 2 describes the active signals used on the 768-Mbit LVQ Family with Asynchronous Static RAM device. Table 2. Signal Descriptions (Sheet 1 of 3) Symbol Type Description ADDRESS INPUTS: Inputs for all die addresses during read and write operations. A[MAX:MIN] Input 64-Mbit Die : AMAX = A21 32-Mbit Die : AMAX = A20 8-Mbit Die : AMAX = A18 A0 is the lowest-order 16-bit wide address. A[25:24] denote high-order addresses reserved for future device densities. DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes on the flash device. FLASH CHIP ENABLE: Low-true input. * * * * * 256-Mbit Die : AMAX= A23 128-Mbit Die : AMAX = A22 D[15:0] Input/ Output F[3:1]-CE# Input F[3:1]-CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. F1-CE# selects or deselects flash die #1; F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects or deselects flash die #3 and is RFU on stacked combinations with only one or two flash dies. SRAM CHIP SELECT: Low-true / high-true input (S-CS1# / S-CS2 respectively). S-CS1# S-CS2 Input When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM Chip Select signals are deasserted, the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked combinations without SRAM die. PSRAM CHIP SELECT: Low-true input. P[2:1]-CS# Input When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die. This ball is an RFU on stacked combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on stacked combinations with two PSRAM dies. This ball is an RFU on stacked combinations without PSRAM or with a single PSRAM. FLASH OUTPUT ENABLE: Low-true input. F[2:1]-OE# Input F[2:1]-OE# low enables the flash output buffers. F[2:1]-OE# high disables the flash output buffers, and places the selected flash outputs in High-Z. F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked combinations with two or three flash die and is RFU on stacked combinations with only one flash die. 18 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Table 2. Signal Descriptions (Sheet 2 of 3) RAM OUTPUT ENABLE: Low-true input. R-OE# Input R-OE# low enables the selected RAM output buffers. R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z. R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only stacked combinations. FLASH WRITE ENABLE: Low-true input. F-WE# Input F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: Low-true input. R-WE# Input R-WE# controls writes to the selected RAM die. R-WE# is available on stacked combinations with PSRAM or SRAM die and is an RFU on flash-only stacked combinations. CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and increments the internal address generator. CLK Input During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, addresses are latched on the rising edge ADV#, or are continuously flow-through when ADV# is kept asserted. WAIT: Output signal. Indicates data is valid in synchronous array or non-array sync flash reads. Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted. With F-CE# and F-OE# at VIL, WAIT's active output is VOL or VOH. WAIT is high-Z if F-CE# or F-OE# is VIH. WAIT Output * In synchronous array or non-array flash read modes, WAIT indicates invalid data when asserted and valid data when deasserted. * In asynchronous flash page read, and all flash write modes, WAIT is deasserted. FLASH WRITE PROTECT: Low-true input. F-WP# Input F-WP# enables/disables the lock-down protection mechanism of the selected flash die. * F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. * F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. ADDRESS VALID: Low-true input. ADV# Input During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous flash read operations, addresses are latched on the rising edge of ADV#, or are continuously flow-through when ADV# is kept asserted. RAM UPPER / LOWER BYTE ENABLES: Low-true input. R-UB# R-LB# Input During RAM read and write cycles, R-UB# low enables the RAM high order bytes on D[15:8], and R-LB# low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die and are RFU on flash-only stacked combinations. FLASH RESET: Low-true input. F-RST# Input F-RST# low initializes flash internal circuitry and disables flash operations. F-RST# high enables flash operation. Exit from reset places the flash in asynchronous read array mode. Datasheet 19 768-Mbit LVQ Family with Asynchronous Static RAM Table 2. Signal Descriptions (Sheet 3 of 3) P-Mode (PSRAM Mode): Low-true input. P-MODE is used to program the configuration register, and enter/exit Low-Power Mode of PSRAM die. P-Mode, P-CRE P-Mode is available on stacked combinations with asynchronous-only PSRAM die. Input P-CRE (PSRAM configuration register enable): High-true input. P-CRE is high, write operations load the refresh control register or bus control register. P-CRE is applicable only on combinations with synchronous PSRAM die. P-Mode, P-CRE s RFU on stacked combinations without PSRAM die. FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables flash program/erase operations. F-VPP, F-VPEN Power Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Erase / program operations at invalid F-VPP (F-VPEN) voltages should not be attempted. Refer to flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products. FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and flash die #3. Write operations are inhibited when F-VCC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F[2:1]-VCC Power F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked combinations with only one flash die. SRAM POWER SUPPLY: Supplies power for SRAM operations. S-VCC Power S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations without SRAM die. PSRAM POWER SUPPLY: Supplies power for PSRAM operations. P-VCC VCCQ VSS RFU DU Power Power Power P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations without PSRAM die. DEVICE I/O POWER: Supply power for the device input and output buffers. DEVICE GROUND: Connect to system ground. Do not float any VSS connection. RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements. Contact Intel regarding the use of balls designated RFU. Don't Use: Do not connect to any other signal, or power supply; must be left floating. 20 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 5.0 5.1 Warning: Maximum Ratings and Operating Conditions Absolute Maximum Ratings Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Table 3. Absolute Maximum Ratings Parameter MIN MAX Unit Notes Temperature under Bias Expanded Storage Temperature Voltage On Any Signal (except F-VCC, VCCQ, F-VPP, S-VCC, and P-VCC) F-VCC Voltage VCCQ, P-VCC and S-VCC Voltage F-VPP Voltage ISH Output Short Circuit Current 1.8V I/O 3.0 V I/O -25 -55 -0.5 -0.2 -0.2 -0.2 -0.2 - +85 +125 +3.6 +2.50 +2.50 +3.60 +10.0 100 C C V V V V V mA 5 5 1,5 1,5 1,5 1,5 1,2,3,5 4,5 NOTES: 1. All specified voltages are relative to VSS. Minimum DC voltage is -0.5 V on input/output signals, -0.2 V on VCCQ and F-VPP signals. During transitions, this level may overshoot to -2.0 V for periods < 20 ns. Maximum DC voltage on F-VCC is VCC + 0.5 V, which during transitions may overshoot to F-Vcc +2.0 V for periods <20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ +0.5 V, which during transitions may overshoot to VCCQ + 2.0V for periods < 20ns. 2. Maximum DC voltage on F-VPP may overshoot to +10.0 V for periods < 20 ns. 3. Flash program/erase voltage (F-VPP) is typically 1.7 V-2.0 V. F-Vpp can be connected to 8.50 V - 9.50 V for 1000 cycles on main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total. Operation with 9.0 V program/erase voltage may reduce flash block cycling capability. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. Absolute DC specifications applies to each flash and RAM die in the SCSP device. Datasheet 21 768-Mbit LVQ Family with Asynchronous Static RAM 5.2 Table 4. Symbol Operating Conditions Extended Temperature Operation Parameter MIN TC MAX MIN MAX MIN MAX Unit Flash + Flash Flash + PSRAM Flash + PSRAM + SRAM2 Operating Temperature Flash Supply Voltage Flash I/O Voltage PSRAM and SRAM Supply Voltage 3.0 V I/O 1.8 V I/O -25 1.7 2.2 1.7 0.9 8.5 +85 2.0 3.3 2.0 2 9.5 -25 1.7 2.7 1.8 0.9 8.5 +85 2.0 3.1 1.95 2 9.5 -25 1.7 2.7 - 0.9 8.5 +85 2.0 3.1 - 2 9.5 C V V V V V F-VCC VCCQ P-VCC S-VCC VPPL1 VPPH 1 F-VPP Voltage Supply (Logic Level) Factory word programming F-VPP NOTES: 1. Flash program/erase voltage (F-VPP) is typically 1.7 V-2.0 V. F-Vpp can be connected to 8.50 V - 9.50 V for 1000 cycles on main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total. Operation with 9.0 V program/erase voltage may reduce flash block cycling capability. 2. SRAM is available only in 3.0 V I/O option. 22 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 6.0 6.1 Electrical Specifications DC Current Characteristics The DC current characteristics referenced in this document are for individual flash and RAM die in the SCSP device. The total device current is determined by sum of the active and inactive currents of each flash and RAM die in the SCSP device. Note: Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for flash DC characteristics not included in this document. SRAM DC characteristics are shown in Table 5. PSRAM DC characteristics are shown in Table 6 on page 24. NOTICE: Individual DC Characteristics of all dies in a SCSP device need to be considered accordingly, depending on the SCSP device stacked combinations and operations. Table 5. Parameter SRAM DC Characteristics 3.0 V SRAM Description Test Conditions MIN MAX Unit S-VCC VDR ICC ICC2 Voltage Range S-VCC for Data Retention Operating Current at minimum cycle time Operating Current at maximum cycle time (1 s) - - IIO = 0 mA IIO = 0 mA S-CS1# S-VCC-0.2V or S-CS2 VSS+0.2V Address/Data toggling at minimum cycle time 2.7 1.5 - - 3.3 - 50 10 V V mA mA ISB Standby Current - 25 A IDR VOH VOL VIH VIL *IIL *ILDR Current in Data Retention mode Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current in Data Retention Mode S-VCC = 1.5 V IOH = -100 A IOL = 100 A, VCCMIN - - -0.2 < VIN < S-VCC+0.2 V -0.2 < VIN < S-VCC+0.2 V S-VCC = VDR - S-VCC 0.1 -0.1 S-VCC 0.4 -0.2 -1 -1 12 - 0.1 S-VCC+ 0.2 0.6 +1 +1 A V V V V A A NOTE: * Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. Datasheet 23 768-Mbit LVQ Family with Asynchronous Static RAM Table 6. PSRAM DC Characteristics P-VCC = 1.8 V to 1.95 V P-VCC = 2.7 V to 3.1 V Unit MIN Typ MAX MIN Typ MAX Test Conditions Parameter Description ICC Operating Current at minimum cycle time Standby Current IOUT=0mA P-CS# P-VCC0.2V,P-Mode P-VCC-0.2V 32-Mbit 64-Mbit 16-Mbit 32Mbit P-CS# P-VCC0.2V, P-Mode 0.2V 64Mbit 8-Mbit 4-Mbit 0-Mbit 16-Mbit 8-Mbit 4-Mbit 0-Mbit - - 35 - - 45 mA A A A A A A A A A A A A - 90 N/A 100 - - 90 110 60 50 40 20 90 80 70 60 20 60 - - - - 100 150 70 60 50 30 110 100 90 80 30 80 - 0.2VCCQ VCCQ+ 0.3 0.2VCCQ +1.0 ISB1 - - - - 60 50 40 20 70 60 50 30 - - - - - - ISB2 Partial Array Refresh Current (Standby Mode 2) N/A - - ISBD Deep Power Down Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Input/Output Leakage Current P-CS# P-VCC0.2V, P-Mode 0.2V 32-Mbit 64-Mbit - 20 N/A 30 - - VOH VOL VIH VIL *IIL IOH = -0.5 mA IOL = 1 mA - - 0.8VCCQ - 0.8VCCQ -0.3 - - - - - 0.2VCCQ VCCQ + 0.3 0.2VCCQ +1.0 0.8VCCQ - 0.8VCCQ -0.3 V V V V A VIN = 0V to VCCQ VI/O = 0V to VCCQ, P-CS# = VIH or R-WE# = VIH or R-OE# = VIH -1.0 - -1.0 - *IOL -1.0 - +1.0 -1.0 - +1.0 A NOTE: * VIN: Input voltage, VI/O: Input/Output voltage. 24 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 7.0 7.1 AC Characteristics SCSP Device AC Test Conditions Figure 8. Transient Equivalent Testing Load Circuit1,2 ZO = 50 Ohms I/O Output 50 Ohms CL = 30pf P_VCC/2 = VCCQ/2 NOTES: 1. Test configuration component value for worst case speed conditions. 2. CL includes jig capacitance. 7.2 SRAM and PSRAM Capacitance SRAM and PSRAM capacitance is shown in Table 7, "SRAM and PSRAM Capacitance" on page 25. Note: Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for flash capacitance details not included in this document. SRAM and PSRAM Capacitance Symbol Parameter MAX (SRAM) MAX (PSRAM) Unit Condition Table 7. CIN COUT Input Capacitance Output Capacitance 6 7 8 10 pF pF VIN = 0 V VOUT = 0 V NOTE: Sampled, not 100% tested. TC = +25 C, f = 1 MHz. 7.3 Note: SRAM AC Read Specifications Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for flash details not included in this document. Datasheet 25 768-Mbit LVQ Family with Asynchronous Static RAM Table 8. SRAM AC Read Specifications # Symbol Parameter MIN MAX Unit Notes R1 R2 R3 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ Read Cycle Time Address to Output Delay S-CS1# to Output Delay S-CS2 to Output Delay R-OE# to Output Delay R-UB#, R-LB# to Output Delay S-CS1# or S-CS2 to Output in Low-Z R-OE# to Output in Low-Z S-CS1# or S-CS2 to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, S-CS1#, S-CS2, or R-OE# Change, whichever Occurs First) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z 70 - - - - - 5 0 0 0 0 0 0 - 70 70 70 35 70 - - 25 25 - - 25 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1,2 1 1,2,3 1,3 NOTES: 1. Sampled, not 100% tested. 2. At any given temperature and voltage condition, tHZ (MAX) is less than tLZ (MAX) for a given device and from device-to-device interconnection. 3. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 26 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Figure 9. SRAM Read Waveform Standby V IH Address Stable VIL V IH R1 Device Address Selection Data Valid S-CS1# VIL V IH R3 R2 R8 S-CS2 VIL R -OE# V IH VIL R9 R4 VIL R7 High Z R6 Valid Output R11 R5 R12 R10 High Z VOH VOL V IH V IH R-WE# V IH DATA R- UB#, R-LB# 7.4 Table 9. SRAM AC Write Specifications SRAM AC Write Specifications (Sheet 1 of 2) # Symbol Parameter MIN MAX Unit Notes W1 W2 W3 W4 W5 W6 W7 tWC tAS tWP tDW tAW tCW tDH Write Cycle Time Address Setup to R-WE# (S-CS1#) and RUB#,R-LB# Going Low R-WE# (S-CS1#) Pulse Width Data to Write Time Overlap Address Setup to R-WE# (S-CS1#) Going High S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) Going High Data Hold from R-WE# (S-CS1#) High 70 0 55 30 60 60 0 - - - - - - - ns ns ns ns ns ns ns 1 3 1 2 Datasheet 27 768-Mbit LVQ Family with Asynchronous Static RAM Table 9. SRAM AC Write Specifications (Sheet 2 of 2) W8 W9 tWR tBW Write Recovery R-UB#, R-LB# Setup to R-WE# (S-CS1#) Going High 0 60 - - ns ns 4 NOTES: 1. A write occurs during the S-CS1# and R-WE# asserted overlap (tWP). The write begins with the latest transition of S-CS1# and R-WE# going low (R-UB# and/or R-LB# already asserted). The write ends at the earliest transition of S-CS1# or R-WE# going high. 2. tCW is measured from S-CS1# going low to the end of a write. 3. tAS is measured from address valid to the beginning of a write. 4. tWR is measured from the end of a write to the address change; tWR applied in case a write ends as SCS1# or R-WE# going high. Figure 10. SRAM Write Waveform Device Address Selection Address Stable VIL V IH W1 W8 Standby V IH ADDRESSES S-CS1# VIL V IH S-CS2 VIL W6 R-OE# V IH VIL W5 W3 R-WE# V IH VIL W7 W4 High Z High Z DATA V OH VOL Data In W2 VIH W9 R- UB#, R-LB# VIH Table 10. SRAM Data Retention Timing Parameter Description MIN MAX Unit tSDR tRDR Data Retention Set-up Time Data Retention Recovery Time 0 70 - - ns ns 28 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Figure 11. SRAM Data Retention Waveform (S-CS1# Controlled) tSDR S-VCC S-VCCmin Data Retention Mode tRDR S-VIHmin VDR S-CS1# VSS Figure 12. SRAM Data Retention Waveform (S-CS2 Controlled) tSDR S-VCC S-CS2 S-VCCMIN Data Retention Mode tRDR VDR VILMAX VSS Datasheet 29 768-Mbit LVQ Family with Asynchronous Static RAM 7.5 PSRAM AC Read Specifications Table 11. PSRAM AC Read Specifications # Symbol Parameter P-VCC = 1.80 V to 1.95 V MIN Read Cycle MAX P-VCC = 2.7 V to 3.1 V MIN MAX Unit Note R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 tRC tAA tCO tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ tASO tOHAH tCHAH tBHAH tCLOL tOLCH tCP tBP tOP tPC tPA Read Cycle Time Address access time P-CS# Low to Output Valid R-OE# Low to Output Valid R-UB#, R-LB# Low to Output Valid P-CS# Low to Output in Low-Z R-OE# Low to Output in Low-Z P-CS# High to Output in High-Z R-OE# High to Output in High-Z Output Hold from Address change R-UB#, R-LB# Low to Output in Low-Z R-UB#, R-LB# High to Output in High-Z Address set to R-OE# low-level R-OE# high-level to address hold P-CS# high-level to address hold R-LB#, R-UB# high-level to address hold P-CS# low-level to R-OE# low-level R-OE# low-level to P-CS# high-level P-CS# high-level pulse width R-UB#, R-LB# high-level pulse width R-OE# high-level pulse width 85* - - - - 10 5 - - 5 5 - 0 -5 0 0 0 60 10 10 - - 85* 85 * 65 - - - - 10 5 - - 5 5 - 0 -5 0 0 0 45 10 10 - - 65 65 45 65 - - 25 25 - - 25 - - - - 10,000 - - - 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 5 65 85* - - 25 25 - - 25 - - - - 10,000 - - - 10,000 5 1 1 1,2 3 3 Page Mode PR1 PR2 Page Cycle Time Page Mode Address Access Time 30 - - 30 18 - - 18 ns ns 4 NOTES: 1. When R13 |R15|, |R16| and R19 18 ns, the minimum value for R15 and R16 are -15 ns. (See also Figure 13, "Conditions for Calculating the Minimum Value for R15 and R16" on page 31.) 2. R16 is specified from when both R-LB# and R-UB# become high-level. 3. R17and R21 (MAX) are applied while P-CS# is being hold at low-level. 4. See Figure 14, "AC Waveform for PSRAM Read Operations" on page 31. 5. * 32-Mbit 1.8V PSRAM initial read access timing specifications changed from 85 ns to 88 ns. 30 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Figure 13. Conditions for Calculating the Minimum Value for R15 and R16 R15, R16 Address R-UB#,R-LB#, P-CS# R-OE# R13 Figure 14. AC Waveform for PSRAM Read Operations R1 Vih Address Vil R2 Vih P-CS# Vil R8 Vih R-UB#, R-LB# Vil R12 Vih R-OE# Vil R9 R7 R11 R6 Voh Data out High-Z Vol Valid Output High-Z R4 R5 R3 R10 NOTE: In a read cycle, P-Mode and R-WE# should be fixed to high-level. Datasheet 31 768-Mbit LVQ Family with Asynchronous Static RAM Figure 15. AC Waveform for PSRAM 8-Word Page Read Operation Vih A3-AMAX Vil Vih A0,A1,A2 Vil P-CS# 000 R2 R3 001 PR1 111 R1 Valid Address R-OE#, R-UB#, R-LB# Voh Data out High-Z Vol PR2 R4 R9 Qn Qn+ 6 Qn+ 7 NOTE: In a page read cycle, P-Mode and R-WE# should be fixed to high-level, and R-UB#, R-LB# are low-level. 7.6 PSRAM AC Write Specifications Table 12. PSRAM AC Write Specifications # Symbol Parameter P-VCC = 1.80 V to 1.95 V P-VCC = 2.7 V to 3.1 V MIN MAX MIN MAX Unit Note W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 tWC tAS tWP tDW tAW tCW tDH tWR tBW tCP tBP tWHP tOHAH tCHAH tBHAH tOES tOEH Write Cycle Time Address Setup Time Write Pulse Width Data valid to Write End Address valid to end of write P-CS# to end of write Data Hold time Write Recovery R-UB#, R-LB# Setup to end of Write P-CS# high-level pulse width R-UB#, R-LB# high-level pulse width R-WE# high-level pulse width R-OE# high-level to address hold P-CS# high-level to address hold R-UB#, R-LB# high-level to address hold R-OE# high-level to R-WE# set R-WE# high-level to R-OE# set 85 0 60 30 70 70 0 0 70 10 10 10 -5 0 0 0 10 - - - - - - - - - - - - - - - 10,000 10,000 65 0 50 35 55 55 0 0 55 10 10 10 -5 0 0 0 10 - - - - - - - - - - - - - - - 10,000 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 1,4 4 4 4 4 4 4 4 1 1 1,2 3 NOTES: 1. When W2 |W14|, |W15| and W10 18 ns, W14 and W15 (MIN) are -15 ns. (See also Figure 16, "Conditions for Calculating the Minimum Value for W14 and W15" on page 33.) 2. W15 is specified from when both R-LB# and R-UB# become high-level. 3. W16 and W17 (MAX) are applied while P-CS# is being hold at low-level. 4. See Figure 17, "AC Waveform for PSRAM Write Operation" on page 33. 32 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Figure 16. Conditions for Calculating the Minimum Value for W14 and W15 W14, W15 Address R-UB#,R-LB#, P-CS# R-WE# W2 W10 Figure 17. AC Waveform for PSRAM Write Operation W1 Vih Address Vil W2 Vih P-CS# Vil W5 W9 W6 W8 Vih R-UB#, R-LB# Vil Vih R-WE# Vil Voh Data I/O Vol Low-Z High-Z W3 W4 Valid Data In W7 High-Z NOTES: 1. During address transition, at least one of the pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should be deasserted. 2. Do not input data to the I/O pins while they are in an output state. 3. In a write cycle, P-Mode and R-OE# should be fixed to high-level. 4. Write operation is done during the overlap time of a low-level P-CS#, R-WE#, R-LB# and/or R-UB#. Datasheet 33 768-Mbit LVQ Family with Asynchronous Static RAM Figure 18. PSRAM Mode Register Update--Timing Waveform R1 Address Highest Address R1 Highest Address W1 Highest Address W1 Highest Address Mode Register Setting P-CS# R-OE# W8 W3 R-WE# W8 W3 W7 W4 Data I/O R-UB#, R-LB# W7 W4 000XH 0000H 8.0 Power and Reset Specifications Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 34 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 9.0 9.1 Design Guide: Operation Overview Bus Operations With F-CE# low and F-RST# high, the flash dies are enabled for normal operations. The flash device internally decodes upper address inputs to determine the accessed partition or block. In an asynchronous read operation, addresses are latched when ADV# transition from VIL to VIH, or continuously flows through if ADV# is held low. In synchronous-burst mode, addresses are latched by the rising edge of ADV# or the next valid CLK edge when ADV# is low. Table 13, "Flash + PSRAM + SRAM Bus Operations" summarizes the bus operations and voltage levels that must be applied to individual flash die in each mode Note: Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares basic asynchronous read and write operations unless otherwise specified. Table 13. Flash + PSRAM + SRAM Bus Operations (Sheet 1 of 2) P-Mode F-RST# S-CS1# F1-CE# F2-CE# D[15:0] R-UB#, R-LB# R-WE# Device F-WE# R-OE# F-VPP S-CS2 P-CS# F-OE# Notes 1,2,3,4 ,5,6,9 1,2,3,4 ,5,6,9 3,4,6 4 4 4 1,2,3,4 ,5,6,9 1,2,3,4 ,5,6,9 3,4,6 4 4 4 Synchronous Array and NonArray Read ADV# Mode WAIT H L H L H Active L X H X X H H H X X X Flash DOUT Flash DOUT Flash DIN Flash High-Z FlashDie #1 (code) Asynchronous Read Write H L H L H Deasserted L X VPP1 or VPP2 High-Z High-Z High-Z H H X X X X X H L H H L Deasserted L X X X X X Output Disable Standby Reset Synchronous Array and NonArray Read Async Read H H L L H X H H X H X X H X X High-Z High-Z High-Z X X X Any xSRAM mode allowed Flash High-Z Flash High-Z H H L L H Deasserted L X H X X H X X X Flash Die #2 DOUT Flash Die #2 DOUT Flash Die #2 DOUT Flash# 2 HighZ H H L L H Deasserted L X Vpp1 or Vpp2 High-Z H X X H X X X Flash Die #2 (data) Write H H L H L Deasserted L H X X H X X X Output Disable H H L H H High-Z X Standby H H H X X High-Z X High-Z Any xSRAM mode allowed Flash #2 High-Z Flash #2 High-Z Reset L X X X X High-Z X High-Z Datasheet 35 768-Mbit LVQ Family with Asynchronous Static RAM Table 13. Flash + PSRAM + SRAM Bus Operations (Sheet 2 of 2) P-Mode S-CS1# F-RST# F1-CE# F2-CE# D[15:0] R-UB#, R-LB# R-WE# Device F-WE# R-OE# S-CS2 P-CS# F-OE# F-VPP Notes 1,3 3 4 4 4 1,3,8 3,8 3,8 4,8 7,8 ADV# Mode WAIT Read X X H H L L X X X X High-Z High-Z X X X X H H H H H H H H H H H L L L H X H H H H L H H X X L H H X H L H X X H L H X L L X X X L L X X PSRAM DOUT PSRAM DIN PSRAM High-Z PSRAM High-Z PSRAM High-Z SRAM DOUT SRAM DIN SRAM High-Z SRAM High-Z SRAM High-Z PSRAM (#1 or #2) Write Output Disable Standby Low-Power Mode Read Any Flash or SRAM mode allowed H H H H H H H L X X X X X X X X X X High-Z High-Z X X X X L L L SRAM Enabled Write Output Disable Standby Data Retention Any Flash or PSRAM mode allowed H Same as SRAM Standby NOTES: 1. WAIT is active during sync burst read when F-CE# and OE# are asserted. WAIT is High-Z if F-CE# or OE# is deasserted. 2. FX-CE# is F1-CE# for Flash #1, F2-CE# for Flash #2, and F3-CE# for Flash #3. FX-OE# is F1-OE# for Flash #1, and F2OE# for Flash #2. 3. For Flash, FX-OE# and F-WE# should never be asserted simultaneously. For PSRAM or SRAM, R-OE# and R-WE# should never be asserted simultaneously. 4. X can be VIL or VIH for inputs and VPP1, VPP2, VPPLK or VPPH for F-Vpp. 5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 6. Refer to Intel Strataflash(R) Wireless Memory System Datasheet for valid DIN during flash writes. 7. The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode. 8. P-Mode is high if PSRAM is in Standby. P-Mode is low if PSRAM is in Low-Power Mode. Please see Section 18.0, "PSRAM Operations" on page 45 for more details on Standby and Low-Power Mode. 9. Data segment flash only operates in asynchronous mode, CLK is ignored and WAIT is deasserted. 9.2 Flash Device Commands and Command Definitions Refer to the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP), 1024-Mbit LV Family Datasheet (order number 253854) for complete descriptions of flash modes and commands, for command bus-cycle definitions, and for flowcharts that illustrate operational routines. Note: Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares basic asynchronous read and write operations unless otherwise specified. 36 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 10.0 Flash Read Operation Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 11.0 Flash Program Operation Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 12.0 Flash Erase Operation Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 13.0 Flash Suspend and Resume Operations Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 14.0 Flash Block Locking and Unlocking Operations Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 15.0 Flash Protection Register Operation Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 16.0 Flash Configuration Operation Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. Datasheet 37 768-Mbit LVQ Family with Asynchronous Static RAM 17.0 17.1 Dual Operation Considerations Product Configurations and Memory Partitioning By default, the first flash die is the first code segment flash die, a fast, eXecute-In-Place (XIP) solution ideal for an instruction fetch application. This portion is the user-selected parameter configuration option, made up of either a 128-Mbit flash die or a 256-Mbit flash die, each containing one parameter partition and several main partitions. The parameter partition contains four 16-KWord parameter blocks and seven 64-KWord main blocks; all main partitions consist of eight 64-KWord main blocks. The large, embedded data segment is a single partition asynchronous page-mode read device that can be made up of multiple dies with densities of 128-Mbit or 256-Mbit. The single partition is made up of four 16-Kword parameter blocks and 64-Kword main blocks. The data segment flash die parameter configuration will always be the opposite of the code segment flash die parameter configuration. See Table 14 on page 39 for examples of configuration options. The code and embedded data portions of the LVQ device are both asymmetrical in blocking. Each memory block features zero-latency block locking. Data integrity is protected even further with the optional use of F-VPP and F-WP# to implement block lock down. The user has the choice of selecting either a top or a bottom parameter partition configuration for the code segment flash die. Depending on the choice of configuration, the data segment flash die in the LVQ device will be parametrically opposed. For instance, if the user selects top parameter configuration for the code segment flash die, the data segment flash die in the package will be configured as bottom parameter configuration, and vice-versa. This ensures the largest number of contiguous main block addresses for software efficiency. The xRAM segment can consist of up to two Pseudo-SRAM (PSRAM) dies and one SRAM die with the following possible densities: * The first PSRAM die can have a density of 64-Mbit or 128-Mbit. * The second PSRAM die can have a density of 64-Mbit or 32-Mbit. * The SRAM die has a density of 8-Mbit. For the code segment, the 128-Mbit flash die has an 8-Mbit partition block and the 256-Mbit flash die has a 16-Mbit partition block. The minimum code + data density combination for the LV18/ LV30 family is 384 Mbit. 38 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM . Figure 19. Top and Bottom Parameter Configurations Top Parameter Partition Block Stacking Convention 1-Code + 1Data 1-Code + 2Data 2-Code + 1Data 2-Code + 2Data Bottom Parameter Partition Block Stacking Convention 1-Code + 1Data 1-Code + 2Data Data (Top) 2-Code + 1Data Data (Top) 2-Code + 2Data Data (Top) Code (Top) Code (Top) Code (Top) Code (Top) Data (Top) Data (Bottom) Data (Top) Code (Top) Code (Bottom) Code (Bottom) Data (Bottom) Code (Bottom) Data (Bottom) Parameter Blocks Main Blocks Data (Bottom) Data (Bottom) Data (Top) Parameter Blocks Main Blocks Code (Bottom) Code (Bottom) Code (Top) Data (Bottom) Code (Bottom) Table 14. LVQ die stacked configuration example (Top / Bottom Parameter) Stacked Configuration Example (Top Parameter) Die Stack Configuration Flash die#1 (user selected) Flash die #2 Flash die #3 Code only Code+Data Code+Data+Data Code+Code+Data Top Top Top Top NA Bottom Top Top NA NA Bottom Bottom Stacked Configuration Example (Bottom Parameter) Die Stack Configuration Flash die#1 (user selected) Flash die #2 Flash die #3 Code Code+Data Code+Data+Data Code+Code+Data Bottom Bottom Bottom Bottom NA Top Bottom Bottom NA NA Top Top 17.2 Product Segment Unique Features The code segment of the 768-Mbit LVQ Family with Asynchronous Static RAM device includes the following enhanced features unless specifically noted otherwise: * 64 unique (Intel pre-programmed) identifier bits and 2,112 user-programmable OTP bits for each code segment flash die. Datasheet 39 768-Mbit LVQ Family with Asynchronous Static RAM * Traditional write, erase, and burst-mode read capabilities of Intel(R) Wireless flash memory. * Simultaneous RWW/RWE operations, enabling a burst read operation in one partition while simultaneous with program or erase operations in other partitions. * Burst-read across partition boundaries, but not across segment dies within the subsystem. Note: User application code is responsible for ensuring that burst-mode reads do not cross into a partition that is in program or erase mode. The embedded data segment includes the following features unless specifically noted otherwise: * High Density offerings of up to 512 Mb designated specifically for large embedded data. * Single partition asynchronous page-mode read operation, allowing for a cost-effective ideal storage format. * Read-while-program or read-while-erase operations can be accomplished with software through program suspend and erase suspend operations. 17.3 Flash Die Memory Map The 768-Mbit LVQ Family with Asynchronous Static RAM device is available in several density and parameter configurations. The memory map is based on the stacking of individual flash die density options of 128 Mbit or 256 Mbit. The memory map shows individual flash die configurations and block/partition allocations. The code segment flash die is made up of 128-Mbit dies or 256-Mbit dies, each containing one parameter partition and several main partitions. The 128-Mbit memory array is divided into sixteen 8-Mbit partitions. Each die density contains one parameter partition and fifteen main partitions. The 8-Mbit top or bottom parameter partition contains four 16-Kword blocks and seven 64-Kword blocks. Each of the remaining fifteen 8-Mbit main partitions contains eight 64-Kword blocks. The 256-Mbit memory array is divided into sixteen 16-Mbit partitions. Each device contains one parameter partition and fifteen main partitions. The 16-Mbit top or bottom parameter partition contains four 16-Kword blocks and fifteen 64-Kword blocks. Each of the remaining fifteen 16Mbit main partitions contains sixteen 64-Kword blocks. The data segment flash die density is made up of 128-Mbit dies or 256-Mbit dies, each containing a single partition architecture made up of four 16-Kword parameter blocks and 64-Kword main blocks. The memory map and partitioning for various flash die combinations, top and bottom parameters and are shown in the following tables: Note: Only 128-Mbit and 256-Mbit flash die densities are used in three flash die SCSP combinations. * * * * Table 17, "Three Flash Dies (Top Parameter) SCSP Memory Map" on page 43 Table 15, "Two Flash Dies (Top Parameter) SCSP Memory Map" on page 41 Table 16, "Two Flash Dies (Bottom Parameter) SCSP Memory Map" on page 42 Table 18, "Three Flash Dies (Bottom Parameter) SCSP Memory Map" on page 44 40 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Table 15. Two Flash Dies (Top Parameter) SCSP Memory Map Flash Die# Die Stack Configuration Partitioning Block Size (KW) 128-Mbit Flash Partition Size (Mbit) Blk# Address Range 256-Mbit Flash Partition Size (Mbit) Blk# Address Range 16 ... 130 7FC000-7FFFFF ... ... 258 FFC000-FFFFFF ... ... Parameter Partition (Partition 0) Code 1 (Top Parameter) 16 64 64 ... 127 7F0000-7F3FFF 126 7E0000-7EFFFF 120 119 ... ... 255 FF0000-FF3FFF 254 FE0000-FEFFFF ... ... Main Partitions (Partition 1 to 7) Main Partitions (Partition 8 to 15) 64 64 64 64 64 ... ... 8 780000-78FFFF 770000-77FFFF ... ... 16 240 F00000-FFFFFF 239 EF0000-EFFFFF ... 64 63 ... 400000-4FFFFF 3F0000-3FFFFF ... 128 800000-80FFFF 127 F70000-F7FFFF ... ... 0 000000-00FFFF 0 000000-00FFFF 130 7F0000-7FFFFF ... ... 258 FF0000-FFFFFF ... ... Data 2 (Bottom Parameter) Single Partition 4 x 16-Kword Parameter Blocks 127 x 64-Kword Main Blocks (128-Mb) 255 x 64-Kword Main Blocks (256-Mb ... 64 64 64 64 64 16 16 ... ... ... 67 66 11 10 ... ... 400000-40FFFF 3F0000-3FFFFF 080000-08FFFF 070000-07FFFF ... ... 131 100000-10FFFF 130 7F0000-7FFFFF 11 10 ... ... 080000-08FFFF 070000-07FFFF ... ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 0 000000-003FFF 0 000000-003FFF Datasheet 41 768-Mbit LVQ Family with Asynchronous Static RAM Table 16. Two Flash Dies (Bottom Parameter) SCSP Memory Map Flash Die# Die Stack Configuration Partitioning Block Size (KW) 128-Mbit Flash Partition Size (Mbit) Blk# Address Range 256-Mbit Flash Partition Size (Mbit) Blk# Address Range 1 Single Partition 4 x 16-Kword Parameter Blocks Data 127 x 64-Kword (Top Main Blocks Parameter) (128-Mb) 255 x 64-Kword Main Blocks (256-Mb 16 ... 16 64 64 64 64 64 ... ... ... 130 67 66 11 10 ... ... ... 7F0000-7FFFFF 400000-40FFFF 3F0000-3FFFFF 080000-08FFFF 070000-07FFFF ... ... ... 258 131 130 11 10 ... ... ... FF0000-FFFFFF 100000-10FFFF 7F0000-7FFFFF 080000-08FFFF 070000-07FFFF ... ... ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 64 Parameter Partition (Partition 0) Code 2 (Bottom Parameter) 130 127 126 ... ... 7FC000-7FFFFF 7F0000-7F3FFF 7E0000-7EFFFF ... ... 258 255 254 ... ... FFC000-FFFFFF FF0000-FF3FFF FE0000-FEFFFF ... ... ... 64 64 64 64 64 16 16 ... ... ... 8 Main Partitions (Partition 1 to 7) Main Partitions (Partition 8 to 15) 120 119 64 63 ... ... 780000-78FFFF 770000-77FFFF 400000-4FFFFF 3F0000-3FFFFF ... ... 16 240 239 128 127 ... F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF F70000-F7FFFF ... ... 0 000000-00FFFF 0 000000-00FFFF 42 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Table 17. Three Flash Dies (Top Parameter) SCSP Memory Map Flash Die# Die Stack Configuration Partitioning Block Partition Size Size (KW) (Mbit) Blk# 128-Mbit Flash Address Range Partition Size (Mbit) 256-Mbit Flash Blk# Address Range 16 ... 130 ... 7FC000-7FFFFF ... 258 ... FFC000-FFFFFF ... Parameter Partition (Partition 0) Code 1 (Top Parameter) 16 64 64 64 64 64 64 16 ... ... ... ... 127 126 120 119 64 63 ... ... ... 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF 400000-4FFFFF 3F0000-3FFFFF ... ... ... 255 254 240 239 128 127 ... ... FF0000-FF3FFF FE0000-FEFFFF F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF F70000-F7FFFF ... ... ... 8 16 Main Partitions (Partition 1 to 7) Main Partitions (Partition 8 to 15) 0 130 ... 000000-00FFFF 7FC000-7FFFFF ... 0 258 ... 000000-00FFFF FFC000-FFFFFF ... Parameter Partition (Partition 0) Code 2 (Top Parameter) 16 64 64 64 64 64 64 64 ... 64 ... ... ... 127 126 120 119 64 63 ... ... ... 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF 400000-4FFFFF 3F0000-3FFFFF ... ... ... 255 254 240 239 128 127 ... ... FF0000-FF3FFF FE0000-FEFFFF F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF F70000-F7FFFF ... ... ... 8 16 Main Partitions (Partition 1 to 7) Main Partitions (Partition 8 to 15) 0 130 67 66 ... ... 000000-00FFFF 7F0000-7FFFFF 400000-40FFFF 3F0000-3FFFFF ... ... 0 258 131 130 ... ... 000000-00FFFF FF0000-FFFFFF 100000-10FFFF 7F0000-7FFFFF ... ... Single Partition Data 3 (Bottom Parameter) 64 64 64 ... ... 4 x 16-Kword Parameter Blocks 127 x 64-Kword Main Blocks (128-Mb) 255 x 64-Kword Main Blocks (256-Mb) 11 10 ... 080000-08FFFF 070000-07FFFF ... 11 10 ... 080000-08FFFF 070000-07FFFF ... 64 16 16 ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 0 000000-003FFF 0 000000-003FFF Datasheet 43 768-Mbit LVQ Family with Asynchronous Static RAM Table 18. Three Flash Dies (Bottom Parameter) SCSP Memory Map Flash Die Stack Die# Configuration Partitioning Block Partition Size Size (KW) (Mbit) Blk# 128-Mbit Flash Address Range Partition Size (Mbit) 256-Mbit Flash Blk# Address Range 16 16 Single Partition 4 x 16-Kword Parameter Blocks 127 x 64-Kword Main Blocks (128-Mb) 255 x 64-Kword Main Blocks (256-Mb) 64 ... ... 130 67 66 ... ... 7F0000-7FFFFF 400000-40FFFF 3F0000-3FFFFF ... ... 258 131 130 ... ... FF0000-FFFFFF 100000-10FFFF 7F0000-7FFFFF ... ... Data 1 (Top Parameter) 64 64 64 64 64 64 ... ... ... 11 10 ... 080000-08FFFF 070000-07FFFF ... 11 10 ... 080000-08FFFF 070000-07FFFF ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 4 3 ... 010000-01FFFF 00C000-00FFFF ... 0 130 ... 000000-003FFF 7FC000-7FFFFF ... 0 258 ... 000000-003FFF FFC000-FFFFFF ... Parameter Partition (Partition 0) Code 2 (Bottom Parameter) 64 64 64 64 64 16 16 64 ... ... ... ... 127 126 120 119 64 63 ... ... ... 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF 400000-4FFFFF 3F0000-3FFFFF ... ... ... 255 254 240 239 128 127 ... ... FF0000-FF3FFF FE0000-FEFFFF F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF F70000-F7FFFF ... ... ... 8 16 Main Partitions (Partition 1 to 7) Main Partitions (Partition 8 to 15) 0 130 ... 000000-00FFFF 7FC000-7FFFFF ... 0 258 ... 000000-00FFFF FFC000-FFFFFF ... Parameter Partition (Partition 0) Code 3 (Bottom Parameter) 64 64 64 64 64 16 16 ... ... ... 127 126 120 119 64 63 ... ... ... 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF 400000-4FFFFF 3F0000-3FFFFF ... ... ... 255 254 240 239 128 127 ... ... FF0000-FF3FFF FE0000-FEFFFF F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF F70000-F7FFFF ... ... ... 8 16 Main Partitions (Partition 1 to 7) Main Partitions (Partition 8 to 15) 0 000000-00FFFF 0 000000-00FFFF 44 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM 18.0 18.1 PSRAM Operations PSRAM Power-up Sequence and Initialization The PSRAM functionality and reliability are independent of the power-up slew rate of the core PVCC. Any power-up slew rate is possible under use conditions. The following power-up sequence and operation should be used before starting normal operation. The PSRAM power-up sequence is represented in Figure 20. At power-up, hold P-Mode low for the period of tVHMH and transition P-CS# from low to high before transitioning P-Mode to a logical high. P-CS# and P-Mode must be held high for the period of tMHCL before normal PSRAM operation is possible once the power up sequence is complete. Figure 20. Timing Waveform for PSRAM Power-Up Sequence Initialization P-CS# tMHCL tCHMH P-Mode tVHMH P-Vcc Vcc (MIN) Normal Operation Table 19. PSRAM Initialization Timing Parameter Symbol MIN MAX Unit s Power application to P-Mode low-level hold P-CS# high-level to P-Mode high-level Following power application, P-Mode highlevel hold to P-CS# low-level tVHMH tCHMH tMHCL 50 0 200 - - - ns s 18.2 PSRAM Mode Register The PSRAM die has an internal register that helps control the Low-Power Mode of the PSRAM. This register is called the Mode Register. A fraction of the PSRAM array can be enabled for refresh by setting the Mode Register. Available fixed, partial-refresh fraction densities are 16 Mbit, 8 Mbit, 4 Mbit and 0 Mbit for all density options. Once the refresh density has been set in the Mode Register, these settings are retained until they are set again while applying the power supply. However, the Mode Register setting will become undefined if the power is turned off; therefore, it is important that the Mode Register is set again after power application. Datasheet 45 768-Mbit LVQ Family with Asynchronous Static RAM 18.2.1 PSRAM Mode Register Setting Since the initial value of the PSRAM Mode Register at power application is undefined, the Mode Register must be set after initialization at power application. When setting the density of partial refresh, data is not guaranteed before entering the Low-Power Mode. (This is the same for reset.) However, since Low-Power Mode is not entered unless P-Mode is a logical low, when partial refresh is not used, it is not necessary to set the Mode Register. Also, when using page read without using partial refresh, it is not necessary to set the Mode Register. The PSRAM Mode Register setting can be entered by successively writing two specific data after two continuous reads of the highest address. The Mode Register setting is a continuous four-cycle operation: two read cycles and two writes cycles. See Table 20 for setting PSRAM Mode Register command sequence. Figure 21, "PSRAM Mode Register Setting Flowchart" on page 47 shows the steps in setting the Mode Register. Figure 18 on page 34 illustrates the timing waveform. Table 20. Setting PSRAM Mode Register Command Sequence Command Sequence Partial refresh density 1st Bus Cycle (Read Cycle) Address Data 2nd Bus Cycle (Read Cycle) Address Data 3rd Bus Cycle (Write Cycle) Address Data 4th Bus Cycle (Write Cycle) Address Data 16-Mbit 8-Mbit 4-Mbit 0-Mbit Highest Address Highest Address Highest Address Highest Address _ _ _ _ Highest Address Highest Address Highest Address Highest Address _ _ _ _ Highest Address Highest Address Highest Address Highest Address 0x00 0x00 0x00 0x00 Highest Address Highest Address Highest Address Highest Address 0x04 0x05 0x06 0x07 46 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Figure 21. PSRAM Mode Register Setting Flowchart START Read Highest Address No by Toggling both P-CS# and R-OE# Read Highest Address No by Toggling both P-CS# and R-OE# No Write to Highest Address No Data=00H No Write to Highest Address No Fail Mode Register setting exit Data=xxH Begin Normal Operation NOTE: xxH=0x04, 0x05, 0x06 or 0x07 18.2.2 Cautions for Setting PSRAM Mode Register For the PSRAM Mode Register setting, the internal counter status is judged by toggling P-CS# and R-OE#. Therefore, toggle P-CS# at every cycle during entry (read cycle twice, write cycle twice), and toggle R-OE# like P-CS# at the first and second read cycles. If incorrect addresses or data are written, or are written in an incorrect order, the setting of the PSRAM Mode Register will be set incorrectly. When the highest address is read consecutively three or more times, the Mode Register setting entries are not performed correctly. Note: Immediately after the highest address is read, the setting of the Mode Register is not performed correctly. Perform the setting of the Mode Register after power application or after accessing other than the highest address. Once the refresh density has been set in the Mode Register, the setting is retained until it is reset again while power is continuously applied. However, the Mode Register setting becomes undefined if the power is turned off. The Mode Register must be reset after after any power cycle. Datasheet 47 768-Mbit LVQ Family with Asynchronous Static RAM 18.3 PSRAM Low-Power Mode In addition to the regular Standby mode with a full density data hold, Low-Power Mode performs partial density data refresh or zero density data refresh. The Low-Power Mode allows the user to turn off sections of the PSRAM die to save refresh current. The PSRAM die is divided into four sections allowing certain sections to be refreshed with P-Mode at a logical-low. In regular Standby mode, both P-CS# and P-Mode are logical-high. But in Low-Power Mode, PMode is a logical-low. In Low-Power Mode, if 0-Mbit setting is set as the density, it is necessary to perform initialization the same way as after applying power in order to return to normal operation from Low-Power Mode. Refer to Figure 20, "Timing Waveform for PSRAM Power-Up Sequence" on page 45 for timing charts. When the density has been to set to 16 Mbit, 8 Mbit, or 4 Mbit in Low-Power Mode, it is not necessary to perform initialization to return to normal operation from Low-Power Mode. Refer to Figure 22, "PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit) Waveform" for timing charts. Figure 22. PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit) Waveform P-Mode tCHML P-CS# Low Power Mode (Partial Array Refresh/Zero Refresh) tMHCL1/tMHCL2 Table 21. PSRAM Low-Power Mode Entry/Exit Timing Parameter Description MIN MAX Unit tCHML tMHCL11 tMHCL22 Low-Power Mode entry, P-CS# high-level to P-Mode# low-level Low-Power Mode (16-, 8-, 4-Mbit hold) exit to normal operation, P-Mode high-level to P-CS# low-level Low-Power Mode (0-Mbit data hold) exit to normal operation, P-Mode high-level to P-CS# low-level 0 30 200 - - - ns ns s NOTES: 1. tMHCL1 is the time it takes to return to normal operation from Low-Power Mode (data hold: 16-, 8-, 4-Mbit). 2. tMHCL2 is the time it takes to return to normal operation from Low-Power Mode (0-Mbit data hold). 48 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Appendix A Write State Machine Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. Appendix B Common Flash Interface Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. Appendix C Flash Flowcharts Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. Datasheet 49 768-Mbit LVQ Family with Asynchronous Static RAM Appendix D Additional Information : Order Number Document Intel StrataFlash(R) Wireless Memory System (LV 18/30 SCSP); 1024-Mbit LVX Family Datasheet Intel StrataFlash(R) Wireless Memory System (LV 18/30 SCSP); 1024-Mbit LV Family Datasheet 253853 253854 NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. For the most current information on Intel(R) Flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash. 50 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Appendix E Ordering Information Figure 23 shows the decoder for the flash-only combinations in the 768-Mbit LVQ Family with Asynchronous Static RAM device. Figure 24 shows the decoder for the flash + RAM combinations in the 768-Mbit LVQ Family with Asynchronous Static RAM device. Figure 23. Decoder for Flash-only Combinations Flash Family 1/2 Flash Family 3/4 Flas h #1 Flas h #2 Flas h #3 NZ 4 8 F 0 0 0 0 LVYDQ0 Device Details Package SCSP Packages: ! RD = SCSP ! NZ = Intel (R) Ultra-Thin SCSP Lead-Free SCSP Packages: ! PF = SCSP ! JZ = Intel (R) Ultra-Thin SCSP 1 = Original version of the products i.e. for this specific example: Speed (Code Die): ! 90 ns aysnc/14 ns sync for 256M flash @ 1.7 V - 2.0 V I/O ! 85 ns aysnc/14 ns sync for 256M flash @ 1.8 V - 2.0 V I/O Speed (Data Die): 170 ns async @ 1.8V-2.0 V I/O 55 ns tAPA Async only Flash Process Technology: 0.13 m ETOXTM VIII Process Product Line Designator 48F = Flash Memory Only Flas h #4 Flash Density 0= 2= 3= 4= No die 64-Mbit 128-Mbit 256-Mbit Pinout Indicator Q= QUAD+ ballout Parameter Location B = Bottom Parameter T = Top Parameter D = Bottom Parameter for Flash Die #1, Top Parameter for Flash Die #2 Product Family L = Intel StrataFlash (R) Wireless Flash Memory (L18/L30) V = Intel StrataFlash(R) Wireless Flash Memory System (LV18/LV30) 0 = No Die Voltage Y = 1.8 Volt Core and I/O Z = 3 Volt I/O, 1.8 Volt Core Datasheet 51 768-Mbit LVQ Family with Asynchronous Static RAM Figure 24. Decoder for Flash + PSRAM Combinations Flash Family 1 Flash Family 2 Flash #1 Flash #2 RAM #1 RD3 8 F 4 4 5 0 LVYBQ0 Package SCSP Packages: ! RD = SCSP ! NZ = Intel (R) Ultra-Thin SCSP Lead-Free SCSP Packages: ! PF = SCSP ! JZ = Intel (R) Ultra-Thin SCSP RAM #2 Device Details 1 = Original version of the products i.e. for this specific example: Speed (Code Die): ! 90 ns aysnc/14 ns sync for 256M flash @ 1.7 V - 2.0 V I/O ! 85 ns aysnc/14 ns sync for 256M flash @ 1.8 V - 2.0 V I/O Speed (Data Die): 170 ns async @ 1.8V-2.0 V I/O 55 ns tAPA Async only Flash Process Technology: 0.13 m ETOXTM VIII Process Package Size: 8 x 11 x 1.2 mm Notes: ! F1-OE# is internally shared between flas die #1 and flash die #2. F2-OE# ball is unused and should be treated as an RFU Product Line Designator 38F = Flash + xRAM Combination Flash Density 0 = No die 3 = 128-Mbit 4 = 256-Mbit RAM Density 0= 2= 4= 5= No die 8-Mbit RAM 32-Mbit RAM 64-Mbit RAM Pinout Indicator Q= QUAD+ ballout Parameter Location B = Bottom Parameter T = Top Parameter D = Bottom Parameter for Flash Die #1, Top Parameter for Flash Die #2 Product Family L = Intel StrataFlash (R) Wireless Flash Memory (L18/L30) LV = Intel StrataFlash(R) Wireless Flash Memory System (LV18/LV30) 0 = No Die Voltage Y = 1.8 Volt Core and I/O Z = 3 Volt I/O, 1.8 Volt Core 52 Datasheet 768-Mbit LVQ Family with Asynchronous Static RAM Table 22. Valid Combinations I/O Voltage Combinations with 128-Mbit Flash Combinations with 256-Mbit Flash RD48F3000L0YTQ0 RD48F3000L0YBQ0 RD38F3040L0YTQ0 RD38F3040L0YBQ0 1.8 V I/O NZ48F4000L0YTQ0 NZ48F4000L0YBQ0 PF48F4000L0YTQ0* PF48F4000L0YBQ0* RD48F4400L0YDQ0 PF48F4400L0YDQ0* RD38F4455LVYTQ0 RD38F4455LVYBQ0 RD48F3000L0ZTQ0 RD48F3000L0ZBQ0 3.0 V I/O RD38F3040L0ZTQ0 RD38F3040L0ZBQ0 RD38F3352LLZDQ0* PF38F3352LLZDQ0* NZ48F4000L0ZTQ0 NZ48F4000L0ZBQ0 RD48F4400L0ZDQ0 RD38F4050L0ZBQ0 RD38F4050L0ZTQ0 NOTE: * These are non-standard product line items and may not be productized. Datasheet 53 768-Mbit LVQ Family with Asynchronous Static RAM 54 Datasheet |
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